Microcomputers are sophisticated, general purpose logic devices which can be programmed to perform a wide variety of useful control functions in industrial and communications equipment, large-scale and medium-scale computer peripheral and terminal hardware, automobiles and other transportation media, amusement and educational devices, household appliances and other consumer goods, and the like. Generally, an entire spectrum of microcomputers is presently available in the commercial marketplace. As the speed of operation, or throughput, of a microcomputer increases, the more valuable and more versatile the microcomputer becomes, since it is able to control a given operation more efficiently and more accurately, or to control a greater number of operations simultaneously, or to control operations requiring relatively fast response times.
The throughput of any given microcomputer is a function of, among other things, the number of machine cycles required to execute a given set of instructions. In the course of designing any computer system, and in particular a microcomputer, a set of instructions is selected which will provide the anticipated programming requirements for the projected market in which the computer system is to be used. The microprocessor, or processor component of a single-chip microcomputer, executes each instruction as a sequence of machine cycles, with the more complex instructions consuming a greater number of machine cycles. The operation of the internal registers and gating circuitry of the microprocessor is synchronized by means of a master clock signal applied to the microprocessor. The master clock signal may actually comprise two or even four clock components; i.e., the microprocessor clock may be two-phase or four-phase. During the basic clock cycle known as the machine cycle, a number of internal processor-related operations may take place simultaneously, including the transfer of digital information from a bus to a register or vice versa, between certain registers, from an address or data buffer to a bus or vice versa, and so forth, or the individual conductors of a bus may each be set to a predetermined logic level, or the contents of a register may be set to a predetermined logic level. The more processor operations occurring within an individual machine cycle the fewer the number of machine cycles required for the execution of a particular instruction. Thus, it is desirable to maximize to the extent possible the number of internal processor operations occurring within a given machine cycle.
It is also desirable, particularly regarding microcomputers intended for marketing in the middle to low end of the price scale, to minimize the microcomputer chip size as much as possible. One major component contributing to the size of the microcomputer chip is the read only memory containing the mask-determinable program or sequence of instructions which controls the operation of the microcomputer in the particular application in which it is to be used. In general, the smaller the physical size of the microcomputer, including the read only memory, the lower the price of the microcomputer.
It is also desirable, especially in the medium to low end microcomputer market, to include in the microprocessor instruction set an instruction for testing the state of a particular bit in the random access memory, or in the read only memory, or in any one of the I/O ports and to branch to a designated location in the instruction sequence if the particular bit is in the desired state. For example, in a microcomputer controlling the operation of an appliance such as a washing machine, a test could be made as to the state of a particular I/O port bit representing the tub fill level. If such bit were determined to be in a state indicating that the tub were filled, a branch could be made to a further memory location in the instruction sequence to an instruction for controlling the further operation of the washing machine, e.g., for starting the agitator.
It is known in the computer art, for example in the instruction set of the IBM 360, to utilize two or more separate instructions to perform a branch if it is determined that a particular bit in a memory location is set to a given desired state. The IBM 360 instruction set includes a "test under mask" instruction in which an 8-bit memory byte may be tested bit-by-bit against an 8-bit mask. Depending upon the outcome of the comparison, a condition code is set to a predetermined state. By means of a sequence branching instruction, conditioned upon the state of the condition code, a branching operation may be performed to another memory location.
The Fairchild F8 microprocessor includes, as one of its branch-on-condition instructions, a BT instruction. One operand of the BT instruction comprises three bits of immediate data (i.e. data which is fixed at assembly time) which is logically OR'd with a three-bit portion of a condition code register known as TMASK. If any resulting bit is a logical "1", an offset contained in an additional operand of the BT instruction is added to the contents of the program counter and a branch is performed to the resulting memory location. The F8 BT instruction has the disadvantage of being based upon a comparison utilizing immediate data rather than upon any desired data (whether fixed or variable) contained at the memory location (ROM, RAM, or I/O port) indicated by one of the operands. As a result such instruction is of limited utility.
The Rockwell PPS-8 microprocessor includes, among its branch-on-condition instructions, BBT and BBF instructions which provide for branching to a memory location designated by one operand if a particular bit in a memory location specified by the contents of a ZX register is set or not set. The BBT and BBF instructions have the disadvantage that the ZX register must be initially loaded by a separate instruction to point to the memory location of the word whose bit is to be tested.
To minimize the cost and increase the throughput of middle to low end microcomputers, it is desirable to provide branch on bit set and branch on bit clear instructions which will provide a branch to a desired location in the instruction sequence depending upon the state of a particular designated bit in a memory word stored either in the RAM, ROM, or an I/O port. It is further desirable that such branching operation be performed in a single instruction execution, since by using a single instruction to designate a branch on bit set or a branch on bit clear operation, the size of the read only memory may be minimized, particularly in the consumer-oriented applications for which middle to low end microcomputers are used. As a result the microcomputer cost is minimized.